1/10 february 2003 n 5v tolerant inputs and outputs n high speed : f max = 150mhz (min.) at v cc =3v n power down protection on inputs and outputs n symmetrical output impedance: |i oh |=i ol = 24ma (min) at v cc =3v n pci bus levels guaranteed at 24 ma n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2.0v to 3.6v (1.5v data retention) n pin and function compatible with 74 series 16374 n latch-up performance exceeds 500ma (jesd 17) n esd performance: hbm > 2000v (mil std 883 method 3015); mm > 200v description the 74LCX16374 is a low voltage cmos 16 bit d-type flip-flop with 3 state outputs non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power and high speed 3.3v applications; it can be interfaced to 5v signal environment for both inputs and outputs. these 16 bit d-type flip-flops are controlled by two clock inputs (nck) and two output enable in- puts(noe ). on the positive transition of the (nck), the nq outputs will be set to the logic state that were setup at the nd inputs. while the (noe ) input is low, the 8 outputs (nq) will be in a normal state (high or low logic level) and while high level the outputs will be in a high impedance state. any output control does not affect the internal op- eration of flip flops; that is, the old data can be re- tained or the new data can be entered even while the outputs are off. it has same speed performance at 3.3v than 5v ac/act family, combined with a lower power consumption. all inputs and outputs are equipped with protec- tion circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74LCX16374 low voltage cmos 16-bit d-type flip-flop (3-state) with 5v tolerant inputs and outputs order codes package tube t & r tssop 74LCX16374ttr tssop pin connection
74LCX16374 2/10 input and output equivalent circuit pin description truth table x : dont care z : high impedance iec logic symbols pin no symbol name and function 1 1oe 3 state output enable input (active low) 2, 3, 5, 6, 8, 9, 11, 12 1q0 to 1q7 3-state outputs 13, 14, 16, 17, 19, 20, 22, 23 2q0 to 2q7 3-state outputs 24 2oe 3 state output enable input (active low) 25 2ck latch enable input 36, 35, 33, 32, 30, 29, 27, 26 2d0 to 2d7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1d0 to 1d7 data inputs 48 1ck latch enable input 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0v) 7, 18, 31, 42 v cc positive supply voltage inputs output oe ck d q hxx z l x no change* lll lhh
74LCX16374 3/10 logic diagram this logic diagram has not to be used to estimate propagation delays absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied 1) i o absolute maximum rating must be observed 2) v o 74LCX16374 4/10 dc specifications dynamic switching characteristics 1) number of outputs defined as "n". measured with "n-1" outputs switching from high to low or low to high. the remaining output is measured in the low state. symbol parameter test condition value unit v cc (v) -40to85c -55to125c min. max. min. max. v ih high level input voltage 2.7to3.6 2.0 2.0 v v il low level input voltage 0.8 0.8 v v oh high level output voltage 2.7to3.6 i o =-100 m av cc -0.2 v cc -0.2 v 2.7 i o =-12 ma 2.2 2.2 3.0 i o =-18 ma 2.4 2.4 i o =-24 ma 2.2 2.2 v ol low level output voltage 2.7to3.6 i o =100 m a 0.2 0.2 v 2.7 i o =12 ma 0.4 0.4 3.0 i o =16 ma 0.4 0.4 i o =24 ma 0.55 0.55 i i input leakage current 2.7to3.6 v i = 0 to 5.5v 5 5 m a i off power off leakage current 0 v i or v o =5.5v 10 10 m a i oz high impedance output leakage current 2.7to3.6 v i =v ih or v il v o = 0 to v cc 5 5 m a i cc quiescent supply current 2.7to3.6 v i =v cc or gnd 20 20 m a v i or v o = 3.6 to 5.5v 20 20 d i cc i cc incr. per input 2.7to3.6 v ih =v cc -0.6v 500 500 m a symbol parameter test condition value unit v cc (v) t a =25c min. typ. max. v olp dynamic low level quiet output (note 1) 3.3 c l =50pf v il =0v,v ih = 3.3v 0.8 v v olv -0.8
74LCX16374 5/10 ac electrical characteristics 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low (t oslh =|t plhm -t plhn |, t oshl =|t phlm -t phln |) 2) parameter guaranteed by design capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /16 (per circuit) symbol parameter test condition value unit v cc (v) c l (pf) r l ( w ) t s = t r (ns) -40 to 85 c -55 to 125 c min. max. min. max. t plh t phl propagation delay time 2.7 50 500 2.5 1.5 6.5 1.5 6.5 ns 3.0 to 3.6 1.5 6.2 1.5 6.2 t pzl t pzh output enable time to high and low level 2.7 50 500 2.5 1.5 6.3 1.5 6.3 ns 3.0 to 3.6 1.5 6.1 1.5 6.1 t plz t phz output disable time from high and low level 2.7 50 500 2.5 1.5 6.2 1.5 6.2 ns 3.0 to 3.6 1.5 6.0 1.5 6.0 t s set-up time, high or low level (dntock) 2.7 50 500 2.5 2.5 2.5 ns 3.0 to 3.6 2.5 2.5 t h hold time, high or low level (dntock) 2.7 50 500 2.5 1.5 1.5 ns 3.0 to 3.6 1.5 1.5 t w ck pulse width, high or low 2.7 50 500 2.5 3.0 3.0 ns 3.0 to 3.6 3.0 3.0 f max clock pulse frequency 3.0 to 3.6 50 500 2.5 170 150 mhz t oslh t oshl output to output skew time (note1, 2) 3.0 to 3.6 50 500 2.5 1.0 1.0 ns symbol parameter test condition value unit v cc (v) t a =25c min. typ. max. c in input capacitance 3.3 v in = 0 to v cc 7pf c out output capacitance 3.3 v in = 0 to v cc 8pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz v in = 0 or v cc 20 pf
74LCX16374 6/10 test circuit c l = 50 pf or equivalent (includes jig and probe capacitance) r l =r1=500 w or equivalent r t =z out of pulse generator (typically 50 w ) waveform 1 : propagation delays, setup and hold times, maximum clock frequency (f=1mhz; 50% duty cycle) test switch t plh ,t phl open t pzl ,t plz 6v t pzh ,t phz gnd
74LCX16374 7/10 waveform 2: output enable and disable time (f=1mhz; 50% duty cycle) waveform 3 : pulse width (f=1mhz; 50% duty cycle)
74LCX16374 8/10 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 d 12.4 12.6 0.488 0.496 e 8.1 bsc 0.318 bsc e1 6.0 6.2 0.236 0.244 e 0.5 bsc 0.0197 bsc k0? 8?0? 8? l 0.50 0.75 0.020 0.030 tssop48 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7065588c
74LCX16374 9/10 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.197 ao 8.7 8.9 0.343 0.350 bo 13.1 13.3 0.516 0.524 ko 1.5 1.7 0.059 0.067 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel tssop48 mechanical data
74LCX16374 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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